In this paper we propose a technique for increasing the rate of failure due to soft errors by carefully choosing the patterns for soft-error detection. It is well known that all circuit nodes are not equally vulnerable to soft error. We propose a metric for measuring vulnerability of a node to soft-error. The pattern selection approach constructs a test set to maximize the node vulnerability metric. In order to facilitate scan based application of these tests, we propose a test-per-clock DFT scheme that allows counting of such errors. The test set thus derived is applied repeatedly to accelerate the soft error rate measurement. Acceleration reported for this technique over random pattern testing on ISCAS-85 benchmarks ranges from 5X to infinity.