This paper proposes a method to perform Failure Mode and Effects Analysis (FMEA) on System-On- Chips (SoC). An automatic tool extracts information from the SoC description and uses them to estimate the intrinsic criticality of invariant and elementary "sensitive zones" and to compute metrics such failure rates, safe failures fraction and diagnostic coverage. A validation flow based on fault injection and fault simulation is included to cross check the FMEA.