Moore's law predicts that soon it will be possible to integrate billions of transistors on a single chip. Currently on-chip communication for multiprocessor system-on-chip (MPSoC) is realized using buses such as AMBA, STbus, and IBM?s Core-connect. On-chip buses are not fundamentally different than computer buses, except that they are designed and optimized to operate entirely within a single chip meaning that wider buses are possible, and there is no constraint to the number of pins. These buses typically include a number of address and data wires, bi-directional signaling for management, and a complex arbitration policy. Since wire delay becomes more critical than computation delay, bus implementations for future SoC will be increasingly hard. For example, placement and routing for on-chip buses is extremely complex due to the large number of wires. Thus, a SoC bus may occupy an area comparable to a processing element.