12th IEEE International On-Line Testing Symposium (IOLTS'06) Lake of Como, Italy July 10-July 12 ISBN: 0-7695-2620-9
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2006.58
It is amazing how chip level integration has progressed to this point that we now have chips that consist of more than a billion transistors. As amazing as this level of integration, we have only been exploiting 2 dimensions (2D) integration only, i.e. transistors are still on a common plane. Obviously, one way to surpass this 2D integration trend is to go three dimensions (3D). The multiple layers of metal interconnects does not qualify as 3D as the transistors are still on the same plane.
Citation:
TM Mak, "Test Challenges for 3D Circuits," iolts, pp.79, 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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