Fault Tolerant System Design Method Based on Self-Checking Circuits

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12th IEEE International On-Line Testing Symposium (IOLTS'06)

Fault Tolerant System Design Method Based on Self-Checking Circuits (PDF)

Lake of Como, Italy

July 10-July 12

ISBN: 0-7695-2620-9

	ASCII Text	x
	Pavel Kubal?, Petr Fiser, Hana Kub?tov?, "Fault Tolerant System Design Method Based on Self-Checking Circuits," IEEE International On-Line Testing Symposium, pp. 185-186, 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006.

	BibTex	x
	@article{ 10.1109/IOLTS.2006.37, author = {Pavel Kubal? and Petr Fiser and Hana Kub?tov?}, title = {Fault Tolerant System Design Method Based on Self-Checking Circuits}, journal ={IEEE International On-Line Testing Symposium}, volume = {0}, year = {2006}, isbn = {0-7695-2620-9}, pages = {185-186}, doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2006.37}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - IEEE International On-Line Testing Symposium TI - Fault Tolerant System Design Method Based on Self-Checking Circuits SN - 0-7695-2620-9 SP185 EP186 A1 - Pavel Kubal?, A1 - Petr Fiser, A1 - Hana Kub?tov?, PY - 2006 KW - null VL - 0 JA - IEEE International On-Line Testing Symposium ER -

Pavel Kubal?, Czech Technical University in Prague, Czech Republic

Petr Fiser, Czech Technical University in Prague, Czech Republic

Hana Kub?tov?, Czech Technical University in Prague, Czech Republic

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2006.37

This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults.

Citation:

Pavel Kubal?, Petr Fiser, Hana Kub?tov?, "Fault Tolerant System Design Method Based on Self-Checking Circuits," iolts, pp.185-186, 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006

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