12th IEEE International On-Line Testing Symposium (IOLTS'06) Error Correction in Arithmetic Operations by I/O Inversion Lake of Como, Italy July 10-July 12 ISBN: 0-7695-2620-9
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2006.31
In this paper we demonstrate how error-correcting addition and multiplication can be performed using selfchecking modules. Our technique is based on the observation that a suitably designed full adder under the presence of any single stuck-at fault produces the fault-free complement of the desired output when fed by the complement of its functional input. We initially apply conventional paritybased error detection in arithmetic modules; upon detection of a fault, this is followed by input inversion, recomputation, and suitable output inversion. We present adder, register and multiplier designs that can be used in this context. We also design a large-scale circuit using this technique (an elliptical filter), outlining the area savings with respect to traditional triple modular redundancy.
Citation:
Petros Oikonomakos, Paul Fox, "Error Correction in Arithmetic Operations by I/O Inversion," iolts, pp.287-292, 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||