12th IEEE International On-Line Testing Symposium (IOLTS'06) Lake of Como, Italy July 10-July 12 ISBN: 0-7695-2620-9
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2006.29
FPGA emulation has proven to be a performance effective method to analyse the behaviour of digital circuits in the presence of soft errors due to SEU effects. In particular, the recently developed Autonomous Emulation techniques allow the classification of thousands and even millions of faults per second. In this paper, an approach to extend the Autonomous Emulation techniques to circuits with embedded memories is presented. The LEON2 processor benchmark is used to demonstrate as an application for the proposed techniques.
Citation:
Mario Garc?a-Valderas, Marta Portela-Garc?, Celia L?pez-Ongil, Luis Entrena, "Emulation-based Fault Injection in Circuits with Embedded Memories," iolts, pp.183-184, 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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