Detection of physical defects (or transient faults) in nanometer products is very challenging. Parametric test, using variable power supply voltage, clock frequency and temperature can be rewarding. However, their impact on digital system performance needs to be evaluated. In this paper, a novel semiempirical analytical model to compute, at logic level, the impact of power supply voltage variations (\DeltaV_D_D) and/or of temperature variations (\DeltaT) on speed response of a digital module is proposed. The model allows low-cost fault simulation. Moreover, it is shown that delay variation can be emulated either by a (\DeltaV_D_D) and/or a \DeltaT_j variations (\DeltaT) The on-chip availability of multipleV_D_D values in products with DVS (Dynamic Voltage Scaling) opens opportunities for novel BIST techniques. A new DVS-based BIST approach is proposed and its ability to detect and diagnose resistive open defects is ascertained.