Design of a Robust 8-Bit Microprocessor to Soft Errors

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12th IEEE International On-Line Testing Symposium (IOLTS'06)

Design of a Robust 8-Bit Microprocessor to Soft Errors (PDF)

Lake of Como, Italy

July 10-July 12

ISBN: 0-7695-2620-9

	ASCII Text	x
	Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis, "Design of a Robust 8-Bit Microprocessor to Soft Errors," IEEE International On-Line Testing Symposium, pp. 195-196, 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006.

	BibTex	x
	@article{ 10.1109/IOLTS.2006.21, author = {Rodrigo Possamai Bastos and Fernanda Lima Kastensmidt and Ricardo Reis}, title = {Design of a Robust 8-Bit Microprocessor to Soft Errors}, journal ={IEEE International On-Line Testing Symposium}, volume = {0}, year = {2006}, isbn = {0-7695-2620-9}, pages = {195-196}, doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2006.21}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - IEEE International On-Line Testing Symposium TI - Design of a Robust 8-Bit Microprocessor to Soft Errors SN - 0-7695-2620-9 SP195 EP196 A1 - Rodrigo Possamai Bastos, A1 - Fernanda Lima Kastensmidt, A1 - Ricardo Reis, PY - 2006 KW - null VL - 0 JA - IEEE International On-Line Testing Symposium ER -

Rodrigo Possamai Bastos, Universidade Federal do Rio Grande do Sul (UFRGS), Brazil

Fernanda Lima Kastensmidt, Universidade Federal do Rio Grande do Sul (UFRGS), Brazil

Ricardo Reis, Universidade Federal do Rio Grande do Sul (UFRGS), Brazil

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2006.21

This work presents a fault-tolerant version of the mass-produced 8-bit microprocessor M68HC11. It is able to tolerate Single Event Transients (SETs) and Single Event Upsets (SEUs). Based on Triple Modular Redundancy (TMR) and Time Redundancy (TR) fault tolerance techniques, a protection scheme was implemented at high level in the sensitive areas of the microprocessor by using only standard gates in order to save design time. Furthermore, fault-tolerant IC design issues and results in area and performance were compared with a non-protected microprocessor version.

Citation:

Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis, "Design of a Robust 8-Bit Microprocessor to Soft Errors," iolts, pp.195-196, 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006

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