Systems on a chip (SoCs) in safety-critical applications need features such as built-in self-test, on-line self-test and error compensation of transient faults. With evershrinking feature size, also built-in self-repair (BISR) may become a must. While BIST and BISR are well understood and frequently implemented for embedded memory blocks, BISR for random logic is by far an unsolved problem. Logic circuits based on fieldprogrammable gate arrays (FPGAs) are a technology base that allows for functional reconfiguration in the field of application. In this paper we investigate on the possibilities and limitations of logic BISR for FPGAs.