Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology

I
IOLTS
2005
11th IEEE International On-Line Testing Symposium
Abstract - Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology

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11th IEEE International On-Line Testing Symposium

Saint Raphael, French Riviera, France

July 06-July 08

ISBN: 0-7695-2406-0

	ASCII Text	x
	Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy, "Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology," On-Line Testing Symposium, IEEE International, pp. 275-280, 11th IEEE International On-Line Testing Symposium, 2005.

	BibTex	x
	@article{ 10.1109/IOLTS.2005.71, author = {Animesh Datta and Saibal Mukhopadhyay and Swarup Bhunia and Kaushik Roy}, title = {Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology}, journal ={On-Line Testing Symposium, IEEE International}, volume = {0}, year = {2005}, issn = {1530-1591}, pages = {275-280}, doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.71}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - On-Line Testing Symposium, IEEE International TI - Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology SN - 1530-1591 SP275 EP280 A1 - Animesh Datta, A1 - Saibal Mukhopadhyay, A1 - Swarup Bhunia, A1 - Kaushik Roy, PY - 2005 KW - null VL - 0 JA - On-Line Testing Symposium, IEEE International ER -

Animesh Datta, Purdue University

Saibal Mukhopadhyay, Purdue University

Swarup Bhunia, Purdue University

Kaushik Roy, Purdue University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.71

In nano-scaled technology large variations in process parameters produces wide delay spread in high performance circuit. In this paper we develop analytical models for yield prediction with respect to delay variation of pipeline design. We have addressed the converse problem of estimating the design space for individual pipe stages based on a target yield. For an example 4 stage pipelined circuit proposed analytical models are verified to predict yield within 2% of results obtained from Monte-Carlo Hspice simulation.

Citation:

Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy, "Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology," iolts, pp.275-280, 11th IEEE International On-Line Testing Symposium, 2005

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