11th IEEE International On-Line Testing Symposium A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features Saint Raphael, French Riviera, France July 06-July 08 ISBN: 0-7695-2406-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.7
Systems on a chip (SoCs) that combine several processor cores plus multiple interconnects are becoming a standard in advanced technologies. For such systems, a comprehensive test strategy that combines external test and self test capabilities as well as on-line and off-line test is becoming a must in order to manage fault mechanisms that are expected for deep sub-micron technologies. Recently, we have developed a hierarchical test concept for SoCs that relies on a test processor as a "hard core". This paper describes an advanced test concept that may serve to support off-line self test as well as advanced on-line test, also including fault diagnosis features.
Citation:
R. Kothe, C. Galke, H. T. Vierhaus, "A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features," iolts, pp.241-246, 11th IEEE International On-Line Testing Symposium, 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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