Impact of Soft Error Challenge on SoC Design

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Y. Zorian Articles by V. A. Vardanian Articles by K. Aleksanyan Articles by K. Amirkhanyan

11th IEEE International On-Line Testing Symposium

Saint Raphael, French Riviera, France

July 06-July 08

ISBN: 0-7695-2406-0

	ASCII Text	x
	Y. Zorian, V. A. Vardanian, K. Aleksanyan, K. Amirkhanyan, "Impact of Soft Error Challenge on SoC Design," IEEE International On-Line Testing Symposium, pp. 63-68, 11th IEEE International On-Line Testing Symposium, 2005.

	BibTex	x
	@article{ 10.1109/IOLTS.2005.36, author = {Y. Zorian and V. A. Vardanian and K. Aleksanyan and K. Amirkhanyan}, title = {Impact of Soft Error Challenge on SoC Design}, journal ={IEEE International On-Line Testing Symposium}, volume = {0}, year = {2005}, issn = {1530-1591}, pages = {63-68}, doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.36}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - IEEE International On-Line Testing Symposium TI - Impact of Soft Error Challenge on SoC Design SN - 1530-1591 SP63 EP68 A1 - Y. Zorian, A1 - V. A. Vardanian, A1 - K. Aleksanyan, A1 - K. Amirkhanyan, PY - 2005 KW - null VL - 0 JA - IEEE International On-Line Testing Symposium ER -

Y. Zorian, Virage Logic Corporation

V. A. Vardanian, Virage Logic Yerevan Branch

K. Aleksanyan, Virage Logic Yerevan Branch

K. Amirkhanyan, Virage Logic Yerevan Branch

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.36

Soft errors are a major challenge to robust design. Conventionally, designs with high level requirements for reliability and availability required protection against soft errors. However, the scaling level reached with today's nanometer technologies is moving the soft error protection requirements to SoC designs for a wide range of applications. This paper discusses the soft error challenge, its implication on SoC design practices and possible approaches to create a robust SoC design.

Citation:

Y. Zorian, V. A. Vardanian, K. Aleksanyan, K. Amirkhanyan, "Impact of Soft Error Challenge on SoC Design," iolts, pp.63-68, 11th IEEE International On-Line Testing Symposium, 2005

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.