11th IEEE International On-Line Testing Symposium Efficient Estimation of SEU Effects in SRAM-Based FPGAs Saint Raphael, French Riviera, France July 06-July 08 ISBN: 0-7695-2406-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.26
SRAM-based FPGAs are becoming very appealing for several applications where high dependability is a mandatory requirement. Unfortunately, the technology of SRAM-based FPGAs is very sensitive to Single Event Upsets (SEUs) and particular concerns arise from SEUs affecting the FPGAs? configuration memory. In this paper we propose a new method for assessing the impact of faults in the configuration memory on the FPGA dependability. The method uses static analysis, thus reducing greatly the time for performing dependability evaluation.
Citation:
M. Sonza Reorda, L. Sterpone, M. Violante, "Efficient Estimation of SEU Effects in SRAM-Based FPGAs," iolts, pp.54-59, 11th IEEE International On-Line Testing Symposium, 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||