Performance test is a powerful technique to identify difficult to detect defects. Recently, the authors have shown that multi-V_DD test schemes may be used in a BIST environment to simulate multi-clock test. Using circuit and logic-level fault simulation it has been demonstrated that the effect of lowering V_DD on the propagation delay time (while keeping invariant the observation pace - at-speed test), is similar to the effect of decreasing the clock period, t_CLK (while keeping nominal V_DD). In this paper, a simple analytical model to represent the dependence of propagation delay time variations of logic elements, Δt_pd, on depleted V_DD (i.e., on ΔV_DD) is introduced. The model allows to back-annotate this dependence to logic-level fault simulation. As clock period decreases (or V_DD decreases) failing vectors inducing errors are identified. Performance histograms, describing the dependence of the number of failing vectors on higher clock speed (or lower V_DD) are used for delay fault detection and defect diagnosis, Basic infrastructures, ISCAS benchmarks and a combinational block of an industrial fleet management system, XTRAN, are used to demonstrate the results.