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11th IEEE International On-Line Testing Symposium
Saint Raphael, French Riviera, France
July 06-July 08
ISBN: 0-7695-2406-0
G. C. Cardarilli, University of Rome "Tor Vergata"
S. Pontarelli, University of Rome "Tor Vergata"
M. Re, University of Rome "Tor Vergata"
A. Salsano, University of Rome "Tor Vergata"
In this paper, an innovative self-checking Reed Solomon encoder architecture is described. The presented architecture exploits some properties of the arithmetic operations in GF(2s) related to the parity of the binary representation of the field elements. Moreover, a method for introducing self-checking capabilities on all the arithmetic structures used in the Reed Solomon encoder is presented. Finally the self-checking encoder architecture has been mapped on a FPGA evaluating its area overhead.
Citation:
G. C. Cardarilli, S. Pontarelli, M. Re, A. Salsano, "Design of a Self Checking Reed Solomon Encoder," iolts, pp.201-202, 11th IEEE International On-Line Testing Symposium, 2005
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