Accumulator-Based Weighted Pattern Generation

I
IOLTS
2005
11th IEEE International On-Line Testing Symposium
Abstract - Accumulator-Based Weighted Pattern Generation

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11th IEEE International On-Line Testing Symposium

Saint Raphael, French Riviera, France

July 06-July 08

ISBN: 0-7695-2406-0

	ASCII Text	x
	I. Voyiatzis, D. Gizopoulos, A. Paschalis, "Accumulator-Based Weighted Pattern Generation," On-Line Testing Symposium, IEEE International, pp. 215-220, 11th IEEE International On-Line Testing Symposium, 2005.

	BibTex	x
	@article{ 10.1109/IOLTS.2005.14, author = {I. Voyiatzis and D. Gizopoulos and A. Paschalis}, title = {Accumulator-Based Weighted Pattern Generation}, journal ={On-Line Testing Symposium, IEEE International}, volume = {0}, year = {2005}, issn = {1530-1591}, pages = {215-220}, doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.14}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - On-Line Testing Symposium, IEEE International TI - Accumulator-Based Weighted Pattern Generation SN - 1530-1591 SP215 EP220 A1 - I. Voyiatzis, A1 - D. Gizopoulos, A1 - A. Paschalis, PY - 2005 KW - null VL - 0 JA - On-Line Testing Symposium, IEEE International ER -

I. Voyiatzis, Technological Educational Institute of Athens

D. Gizopoulos, University of Piraeus

A. Paschalis, University of Athens

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.14

Weighted pseudorandom BIST schemes have been efficiently utilized in order to drive down the number of vectors required to achieve complete fault coverage in Built in Self Test (BIST) applications. Sets of patterns comprising weights 0, 0.5 and 1 have been successfully utilized within the weighted pattern generation paradigm.

In this paper an accumulator-based scheme is presented, that generates set of patterns with weights 0, 0.5 and 1. Since accumulators and ALUs are commonly found in current VLSI chips, the presented scheme can be efficiently utilized to drive down the hardware of BIST pattern generation.

Citation:

I. Voyiatzis, D. Gizopoulos, A. Paschalis, "Accumulator-Based Weighted Pattern Generation," iolts, pp.215-220, 11th IEEE International On-Line Testing Symposium, 2005

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