2006 First International Multi-Symposiums on Computer and Computational Sciences
CoarseZ Buffer Bandwidth Model in 3D Rendering Pipeline
Hangzhou, Zhejiang, China
June 20-June 24
ISBN: 0-7695-2581-4
Ke Yang, Zhejiang University, China
Ke Gao, Zhejiang University, China
Depth traffic occupies a major portion of 3D graphics memory bandwidth. In order to reduce depth reading, we propose employing a low-resolution depth buffer, namely CoarseZ buffer, for tile-level depth culling before perpixel test. The maximum depth of a tile is stored in the corresponding entry of CoarseZ buffer. Simulation results show that a small CoarseZ buffer can achieve remarkably high culling rate and significantly reduce z-reading bandwidth. We build a model that quantifies the influence of the CoarseZ design parameters on its efficiency and bandwidth. Test results of industrial benchmarks show that CoarseZ with tile size of 4 and bit depth of 16 can be a best selection to reduce memory bandwidth.
Citation:
Ke Yang, Ke Gao, Jiaoying Shi, Xiaohong Jiang, Hua Xiong, "CoarseZ Buffer Bandwidth Model in 3D Rendering Pipeline," imsccs, vol. 1, pp.737-742, 2006 First International Multi-Symposiums on Computer and Computational Sciences, 2006