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2006 First International Multi-Symposiums on Computer and Computational Sciences
Verification Environment for a SCMP Architecture
Hangzhou, Zhejiang, China
June 20-June 24
ISBN: 0-7695-2581-4
ASCII Text
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Wenbin Yao, Nianmin Yao, Shaobin Cai, Jun Ni, "Verification Environment for a SCMP Architecture," Computer and Computational Sciences, International Multi-Symposiums on, vol. 2, pp. 787-791, 2006 First International Multi-Symposiums on Computer and Computational Sciences, 2006.
 
 
BibTex
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@article{ 10.1109/IMSCCS.2006.283,
author = {Wenbin Yao and Nianmin Yao and Shaobin Cai and Jun Ni},
title = {Verification Environment for a SCMP Architecture},
journal ={Computer and Computational Sciences, International Multi-Symposiums on},
volume = {2},
year = {2006},
isbn = {0-7695-2581-4},
pages = {787-791},
doi = {http://doi.ieeecomputersociety.org/10.1109/IMSCCS.2006.283},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Computer and Computational Sciences, International Multi-Symposiums on
TI - Verification Environment for a SCMP Architecture
SN - 0-7695-2581-4
SP787
EP791
A1 - Wenbin Yao,
A1 - Nianmin Yao,
A1 - Shaobin Cai,
A1 - Jun Ni,
PY - 2006
KW - null
VL - 2
JA - Computer and Computational Sciences, International Multi-Symposiums on
ER -
 
Wenbin Yao, Harbin Engineering University, China
Nianmin Yao, Harbin Engineering University, China
Shaobin Cai, Harbin Engineering University, China
Jun Ni, Harbin Engineering University, China
The computer architecture of Single-chip multiprocessor (SCMP) is one of important research topics in developing the next-generation of computer hardware. A verification environment in the SCMP architecture, base of RISC microprocessor, acts as a functional verification simulator that elaborates its functions. This paper reports a simulation of the operational behavior in terms of function units. The simulation was in the mode of cycle-by-cycle when programs execute. The results of the SCMP simulation show that the simulation and its implementation can be used to effectively study the feasibility and applicability of the SCMP architecture.
Citation:
Wenbin Yao, Nianmin Yao, Shaobin Cai, Jun Ni, "Verification Environment for a SCMP Architecture," imsccs, vol. 2, pp.787-791, 2006 First International Multi-Symposiums on Computer and Computational Sciences, 2006
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