Optimized Design of Interconnected Bus on Chip for Low Power

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Donghai Li Articles by Guangsheng Ma Articles by Gang Feng

2006 First International Multi-Symposiums on Computer and Computational Sciences

Hangzhou, Zhejiang, China

June 20-June 24

ISBN: 0-7695-2581-4

	ASCII Text	x
	Donghai Li, Guangsheng Ma, Gang Feng, "Optimized Design of Interconnected Bus on Chip for Low Power," Computer and Computational Sciences, International Multi-Symposiums on, vol. 2, pp. 298-302, 2006 First International Multi-Symposiums on Computer and Computational Sciences, 2006.

	BibTex	x
	@article{ 10.1109/IMSCCS.2006.247, author = {Donghai Li and Guangsheng Ma and Gang Feng}, title = {Optimized Design of Interconnected Bus on Chip for Low Power}, journal ={Computer and Computational Sciences, International Multi-Symposiums on}, volume = {2}, year = {2006}, isbn = {0-7695-2581-4}, pages = {298-302}, doi = {http://doi.ieeecomputersociety.org/10.1109/IMSCCS.2006.247}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer and Computational Sciences, International Multi-Symposiums on TI - Optimized Design of Interconnected Bus on Chip for Low Power SN - 0-7695-2581-4 SP298 EP302 A1 - Donghai Li, A1 - Guangsheng Ma, A1 - Gang Feng, PY - 2006 KW - power optimization KW - self transition KW - coupled transition KW - interconnected bus VL - 2 JA - Computer and Computational Sciences, International Multi-Symposiums on ER -

Donghai Li, Harbin Engineering University, China

Guangsheng Ma, Harbin Engineering University, China

Gang Feng, Harbin Engineering University, China

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IMSCCS.2006.247

In this paper, we firstly propose an on-chip bus power consumption model, which includes the self transition power dissipated on the signal lines and the coupled transition power dissipated between every two signal lines. And then a new heuristic algorithm is proposed to determine a physical order of signal lines in bus. Experimental results show that average power saving 26.85%.

Index Terms:

power optimization, self transition, coupled transition, interconnected bus

Citation:

Donghai Li, Guangsheng Ma, Gang Feng, "Optimized Design of Interconnected Bus on Chip for Low Power," imsccs, vol. 2, pp.298-302, 2006 First International Multi-Symposiums on Computer and Computational Sciences, 2006

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.