A VLSI Architecture for Weight Perturbation on Chip Learning Implementation

I
IJCNN
2000
IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 4
Abstract - A VLSI Architecture for Weight Perturbation on Chip Learning Implementation

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	Similar Articles Articles by F. Diotalevi Articles by M. Valle Articles by G.M. Bo Articles by D.D. Caviglia

IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 4

Como, Italy

July 24-July 27

ISBN: 0-7695-0619-4

	ASCII Text	x
	F. Diotalevi, M. Valle, G.M. Bo, D.D. Caviglia, "A VLSI Architecture for Weight Perturbation on Chip Learning Implementation," Neural Networks, IEEE - INNS - ENNS International Joint Conference on, vol. 4, pp. 4219, IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 4, 2000.

	BibTex	x
	@article{ 10.1109/IJCNN.2000.860776, author = {F. Diotalevi and M. Valle and G.M. Bo and D.D. Caviglia}, title = {A VLSI Architecture for Weight Perturbation on Chip Learning Implementation}, journal ={Neural Networks, IEEE - INNS - ENNS International Joint Conference on}, volume = {4}, year = {2000}, issn = {1098-7576}, pages = {4219}, doi = {http://doi.ieeecomputersociety.org/10.1109/IJCNN.2000.860776}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Neural Networks, IEEE - INNS - ENNS International Joint Conference on TI - A VLSI Architecture for Weight Perturbation on Chip Learning Implementation SN - 1098-7576 SP EP A1 - F. Diotalevi, A1 - M. Valle, A1 - G.M. Bo, A1 - D.D. Caviglia, PY - 2000 VL - 4 JA - Neural Networks, IEEE - INNS - ENNS International Joint Conference on ER -

F. Diotalevi, University of Genova

M. Valle, University of Genova

G.M. Bo, University of Genova

D.D. Caviglia, University of Genova

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IJCNN.2000.860776

In this paper we present the analog on-chip learning architecture of a gradient descent learning algorithm: the Weight Perturbation learning algorithm. From the circuit implementation point of view, our approach is based on current mode and trans-linear operated circuits. The proposed architecture is very efficient in terms of speed, size, precision and power consumption; moreover, it exhibits also high scalability and modularity.

Citation:

F. Diotalevi, M. Valle, G.M. Bo, D.D. Caviglia, "A VLSI Architecture for Weight Perturbation on Chip Learning Implementation," ijcnn, vol. 4, pp.4219, IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN'00)-Volume 4, 2000

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