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2006 International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP'06)
VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design
Pasadena, California, USA
December 18-December 20
ISBN: 0-7695-2745-0
ASCII Text
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Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun, "VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design," Intelligent Information Hiding and Multimedia Signal Processing, International Conference on, pp. 587-592, 2006 International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP'06), 2006.
 
 
BibTex
x
 
@article{ 10.1109/IIH-MSP.2006.173,
author = {Zheng Shen and Hu He and Yanjun Zhang and Yihe Sun},
title = {VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design},
journal ={Intelligent Information Hiding and Multimedia Signal Processing, International Conference on},
volume = {0},
year = {2006},
isbn = {0-7695-2745-0},
pages = {587-592},
doi = {http://doi.ieeecomputersociety.org/10.1109/IIH-MSP.2006.173},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Intelligent Information Hiding and Multimedia Signal Processing, International Conference on
TI - VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design
SN - 0-7695-2745-0
SP587
EP592
A1 - Zheng Shen,
A1 - Hu He,
A1 - Yanjun Zhang,
A1 - Yihe Sun,
PY - 2006
KW - null
VL - 0
JA - Intelligent Information Hiding and Multimedia Signal Processing, International Conference on
ER -
 
Zheng Shen, Tsinghua University, China
Hu He, Tsinghua University, China
Yanjun Zhang, Tsinghua University, China
Yihe Sun, Tsinghua University, China
This paper describes a novel video specific instruction set architecture for ASIP design. With SIMD (Single Instruction Multiple Data) instructions, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS ISA (Video Specific Instruction Set Architecture), other DSPs (digital signal processors) and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS ISA improves the processor?s performance by approximate 5x on H.263 encoding, and VS ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT.
Citation:
Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun, "VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design," iih-msp, pp.587-592, 2006 International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP'06), 2006
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