Design of High-speed Parallel Arithmetic Algorithms and Architectures

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Valentina Markova

1st International Workshop on Distributed Interactive Simulation and Real-Time Applications (DIS-RT '97)

Eilat, ISRAEL

January 09-January 10

ISBN: 0-8186-7773-2

	ASCII Text	x
	Valentina Markova, "Design of High-speed Parallel Arithmetic Algorithms and Architectures," Distributed Interactive Simulation and Real-Time Applications, International Workshop on, pp. 57, 1st International Workshop on Distributed Interactive Simulation and Real-Time Applications (DIS-RT '97), 1997.

	BibTex	x
	@article{ 10.1109/IDSRTA.1997.568658, author = {Valentina Markova}, title = {Design of High-speed Parallel Arithmetic Algorithms and Architectures}, journal ={Distributed Interactive Simulation and Real-Time Applications, International Workshop on}, volume = {0}, year = {1997}, isbn = {0-8186-7773-2}, pages = {57}, doi = {http://doi.ieeecomputersociety.org/10.1109/IDSRTA.1997.568658}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Distributed Interactive Simulation and Real-Time Applications, International Workshop on TI - Design of High-speed Parallel Arithmetic Algorithms and Architectures SN - 0-8186-7773-2 SP EP A1 - Valentina Markova, PY - 1997 VL - 0 JA - Distributed Interactive Simulation and Real-Time Applications, International Workshop on ER -

Valentina Markova, Supercomputer Software Department

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IDSRTA.1997.568658

This paper is oriented to algorithm for computing a sum of products realizing a fundamental compound operation multiply and add of high-speed arithmetic. Two new cellular pipelined algorithms and architectures (20 and 30) are proposed. The initial data and results are binary signed-digit integers. The multipliers are loaded digit serially, the multiplicands - digit parallelly, the results are produced digit parallelly. The design is performed in terms of cellular technology, based on an original model of distributed computation (Parallel Substitution Algorithm). The time and structural complexity is obtained.

Citation:

Valentina Markova, "Design of High-speed Parallel Arithmetic Algorithms and Architectures," dis-rt, pp.57, 1st International Workshop on Distributed Interactive Simulation and Real-Time Applications (DIS-RT '97), 1997

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.