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1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
Implementation of a BIC Monitor in a New Analog BIST Structure.
Washington, DC
October 24-October 25
ISBN: 0-8186-7655-8
M. Sidiropulos, Technical University of Brno
V. Stopjakova, Slovak Technical University
The last step in the development of a BIST structure employing a new self-test technique for analog circuits is presented in this paper, namely the design and implementation of a suitable built-in supply current (BIC) monitor. The new self-test technique, based on power supply current monitoring, takes advantage of the redundancy in the structure of fully balanced circuits.. The new technique requires a special BIC monitor that provides appropriate signals for a successful fault detection. The BIC monitor, presented in this paper, is based on a second generation current conveyor CCII+, and offers an accurate measurement of supply currents with a minimal supply voltage degradation. The BIC monitor circuit was evaluated using fault simulations, which show a reasonable fault coverage. An implementation of the new BIC monitor in an analog BIST structure is finally described.
Index Terms:
BIC monitor, Analog self-test, BIST, IDD Monitoring, Fully differential structures, VLSI, ASIC, CMOS.
Citation:
M. Sidiropulos, V. Stopjakova, H. Manhaeve, "Implementation of a BIC Monitor in a New Analog BIST Structure.," iddq, pp.59, 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96), 1996
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