A lithography driven layout (LDL) design approach is presented. The approach adds upon the conventional layout optimisation criterions to include the effects of lithographic complexity of the future IC technologies. We analyse the various tradeoffs between the design and lithographic requirements for the IC layouts. Based on this, various LDL, design rules are identified that leads to a good compromise between conflicting litho and design requirements. These LDL rules goes beyond the common design for manufacturability rules as they try to reduce the mask cost and extend the lifetime of existing litho-tools. A set of standard-cell layouts designed in 65nm CMOS technology are analysed for their litho-printability. Based on this, LDL design constraints are identified which simplify lithography and have limited impact on design area. The impact of such LDL rules on the performance, cost, and litho printability of IC layouts is presented.