Constrained Floorplanning with Whitespace

V
VLSID
2004
17th International Conference on VLSI Design
Abstract - Constrained Floorplanning with Whitespace

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17th International Conference on VLSI Design

Mumbai, India

January 05-January 09

ISBN: 0-7695-2072-3

	ASCII Text	x
	Yan Feng, Dinesh Mehta, "Constrained Floorplanning with Whitespace," VLSI Design, International Conference on, pp. 969, 17th International Conference on VLSI Design, 2004.

	BibTex	x
	@article{ 10.1109/ICVD.2004.1261056, author = {Yan Feng and Dinesh Mehta}, title = {Constrained Floorplanning with Whitespace}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {969}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261056}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Constrained Floorplanning with Whitespace SN - 1063-9667 SP EP A1 - Yan Feng, A1 - Dinesh Mehta, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Yan Feng, Colorado School of Mines

Dinesh Mehta, Colorado School of Mines

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261056

This paper considers the constrained floorplanning problem in the context of a design scenario where floorplans are required to contain some white space to facilitate subsequent buffer insertion. An elegant bounded iterative methodology for floorplan-refinement based on the min-cost max-flow formulation of Feng et al [1] augmented by a heuristic area-redistribution algorithm is presented. This approach results in substantially bet-ter quality floorplans than previously reported as substantiated by our experimental results.

Citation:

Yan Feng, Dinesh Mehta, "Constrained Floorplanning with Whitespace," vlsid, pp.969, 17th International Conference on VLSI Design, 2004

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