Energy Model Based Macrocell Placement for Wirelength Minimization

V
VLSID
2004
17th International Conference on VLSI Design
Abstract - Energy Model Based Macrocell Placement for Wirelength Minimization

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	Similar Articles Articles by Stelian Alupoaei Articles by Srinivas Katkoori

17th International Conference on VLSI Design

Mumbai, India

January 05-January 09

ISBN: 0-7695-2072-3

	ASCII Text	x
	Stelian Alupoaei, Srinivas Katkoori, "Energy Model Based Macrocell Placement for Wirelength Minimization," VLSI Design, International Conference on, pp. 713, 17th International Conference on VLSI Design, 2004.

	BibTex	x
	@article{ 10.1109/ICVD.2004.1261010, author = {Stelian Alupoaei and Srinivas Katkoori}, title = {Energy Model Based Macrocell Placement for Wirelength Minimization}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {713}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261010}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Energy Model Based Macrocell Placement for Wirelength Minimization SN - 1063-9667 SP EP A1 - Stelian Alupoaei, A1 - Srinivas Katkoori, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Stelian Alupoaei, University of South Florida

Srinivas Katkoori, University of South Florida

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261010

We propose a new iterative approach that models the wirelength minimization problem as a minimum (potential) energy problem. The cell energy is the sum of the net energy (analogous to the spring elastic energy) and the overlap potential energy (analogous to the gravitational potential energy). Energy-based model is shown to be superior to the force-directed model.

Citation:

Stelian Alupoaei, Srinivas Katkoori, "Energy Model Based Macrocell Placement for Wirelength Minimization," vlsid, pp.713, 17th International Conference on VLSI Design, 2004

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