Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors

V
VLSID
2004
17th International Conference on VLSI Design
Abstract - Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Ashis Kumar Mal Articles by Anindya Sundar Dhar

17th International Conference on VLSI Design

Mumbai, India

January 05-January 09

ISBN: 0-7695-2072-3

	ASCII Text	x
	Ashis Kumar Mal, Anindya Sundar Dhar, "Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors," VLSI Design, International Conference on, pp. 666, 17th International Conference on VLSI Design, 2004.

	BibTex	x
	@article{ 10.1109/ICVD.2004.1260999, author = {Ashis Kumar Mal and Anindya Sundar Dhar}, title = {Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {666}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260999}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors SN - 1063-9667 SP EP A1 - Ashis Kumar Mal, A1 - Anindya Sundar Dhar, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Ashis Kumar Mal, IIT Kharagpur

Anindya Sundar Dhar, IIT Kharagpur

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260999

This paper describes an analog VLSI architecture, to compute discrete cosine transform(DCT), using switched-switched capacitor blocks. The scheme operates from the general expression of DCT where input samples are multiplied by all the DCT coefficients simultaneously using an array of capacitors. These multiplied values are then switched parallely with the help of a cross-point switch, to different integrators to perform multiplication and accumulation(MAC). It can be used to compute DHT, DST and DFT and also its inverses. Proposed architecture is very simple to implement and sutable where silicon area and power issues are important with some compromise on accuracy.

Citation:

Ashis Kumar Mal, Anindya Sundar Dhar, "Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors," vlsid, pp.666, 17th International Conference on VLSI Design, 2004

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.