17th International Conference on VLSI Design A 800 MHz System-on-Chip for Wireless Infrastructure Applications Mumbai, India January 05-January 09 ISBN: 0-7695-2072-3
The 800MHz System-on-Chip implements the C64x VLIW DSP VelociTI.2TM Architecture and delivers 6400 MIPS, 3200 16-bit MMACs, 6400 8-bit MMACs at 0.17 mW/MMAC (8 bit). The chip is implemented in state of the art 90 nm CMOS technology with 7-layer copper metalization. The core dissipates 1080 mW at 800 MHz, 1.2V. The system-on-chip is targeted for high performance wireless infrastructure application. It has an 8-way VLIW DSP core, a 2-level memory system, and an I/O bandwidth of 3.2GB/s.
Citation:
Sanjive Agarwala, Paul Wiley, Arjun Rajagopal, Anthony Hill, Raguram Damodaran, Lewis Nardini, Tim Anderson, Steven Mullinnix, Jose Flores, Heping Yue, Abhijeet Chachad, John Apostol, Kyle Castille, Usha Narasimha, Tod Wolf, NS Nagaraj, Manjeri Krishnan, Luong Nguyen, Todd Kroeger, Mike Gill, Peter Groves, Bill Webster, Joel Graber, Christine Karlovich, "A 800 MHz System-on-Chip for Wireless Infrastructure Applications," vlsid, pp.381, 17th International Conference on VLSI Design, 2004 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||