Automated Architectural Optimization of Digital FIR Filters

V
VLSID
2004
17th International Conference on VLSI Design
Abstract - Automated Architectural Optimization of Digital FIR Filters

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17th International Conference on VLSI Design

Mumbai, India

January 05-January 09

ISBN: 0-7695-2072-3

	ASCII Text	x
	Ronald W. Mehler, Dian Zhou, "Automated Architectural Optimization of Digital FIR Filters," VLSI Design, International Conference on, pp. 177, 17th International Conference on VLSI Design, 2004.

	BibTex	x
	@article{ 10.1109/ICVD.2004.1260921, author = {Ronald W. Mehler and Dian Zhou}, title = {Automated Architectural Optimization of Digital FIR Filters}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {177}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260921}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Automated Architectural Optimization of Digital FIR Filters SN - 1063-9667 SP EP A1 - Ronald W. Mehler, A1 - Dian Zhou, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Ronald W. Mehler, The University of Texas at Dallas

Dian Zhou, The University of Texas at Dallas

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260921

Using a newly developed fine-grained architectural synthesizer for digital finite impulse response (FIR) filters, the authors present a near-optimal strategy for coefficient manipulation that runs linearly with filter length. The synthesizer operates at a high level of abstraction, balancing speed, area and power goals to generate a circuit optimized for specified parameters. Experimental results show that it is highly competitive with the best efforts of human designers and other automated procedures.

Citation:

Ronald W. Mehler, Dian Zhou, "Automated Architectural Optimization of Digital FIR Filters," vlsid, pp.177, 17th International Conference on VLSI Design, 2004

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