loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
17th International Conference on VLSI Design
Towards The Complete Elimination of Gate/Switch Level Simulations
Mumbai, India
January 05-January 09
ISBN: 0-7695-2072-3
ASCII Text
x 
 
Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham, "Towards The Complete Elimination of Gate/Switch Level Simulations," VLSI Design, International Conference on, pp. 115, 17th International Conference on VLSI Design, 2004.
 
 
BibTex
x
 
@article{ 10.1109/ICVD.2004.1260913,
author = {Narayanan Krishnamurthy and Jayanta Bhadra and Magdy S. Abadir and Jacob A. Abraham},
title = {Towards The Complete Elimination of Gate/Switch Level Simulations},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2004},
issn = {1063-9667},
pages = {115},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260913},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Towards The Complete Elimination of Gate/Switch Level Simulations
SN - 1063-9667
SP
EP
A1 - Narayanan Krishnamurthy,
A1 - Jayanta Bhadra,
A1 - Magdy S. Abadir,
A1 - Jacob A. Abraham,
PY - 2004
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Narayanan Krishnamurthy, Motorola Inc.
Jayanta Bhadra, Motorola Inc.
Magdy S. Abadir, Motorola Inc.
Jacob A. Abraham, The University of Texas at Austin
This paper presents the reasoning behind eliminating full-chip gate/switch-level simulations for microprocessors/ digital system designs and utilizing RTL models for the purpose, provided formal boolean equivalence between RTL and gate/switch-level models have been established using symbolic simulation for all blocks that comprise the chip. No logic bug should go undetected if only RTL models are used for full chip simulations provided existing design methodologies are enhanced to incorporate a constraints checking ow coupled with a rigorous circuit metastability/contention prevention flow.
Citation:
Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham, "Towards The Complete Elimination of Gate/Switch Level Simulations," vlsid, pp.115, 17th International Conference on VLSI Design, 2004
Usage of this product signifies your acceptance of the Terms of Use.