CMOS Scaling for sub-90 nm to sub-10 nm

V
VLSID
2004
17th International Conference on VLSI Design
Abstract - CMOS Scaling for sub-90 nm to sub-10 nm

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17th International Conference on VLSI Design

Mumbai, India

January 05-January 09

ISBN: 0-7695-2072-3

	ASCII Text	x
	Hiroshi Iwai, "CMOS Scaling for sub-90 nm to sub-10 nm," VLSI Design, International Conference on, pp. 30, 17th International Conference on VLSI Design, 2004.

	BibTex	x
	@article{ 10.1109/ICVD.2004.1260899, author = {Hiroshi Iwai}, title = {CMOS Scaling for sub-90 nm to sub-10 nm}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {30}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260899}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - CMOS Scaling for sub-90 nm to sub-10 nm SN - 1063-9667 SP EP A1 - Hiroshi Iwai, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Hiroshi Iwai, Tokyo Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260899

Recently, CMOS downsizing has been accelerated very aggressively in both production and reseach level, and even transistor operation of a 6 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing such small-geometry MOSFETs into large scale integrated circuits, and it is still questionable whether we can successfully introduce sub-10 nm CMOS LSIs into market or not. In this paper, limitation and its possible causes for the downscaling of CMOS towards sub-10 nm are discussed with consideration of past CMOS predictions for the limitation.

Citation:

Hiroshi Iwai, "CMOS Scaling for sub-90 nm to sub-10 nm," vlsid, pp.30, 17th International Conference on VLSI Design, 2004

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