Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy

V
VLSID
2003
16th International Conference on VLSI Design
Abstract - Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Vani Prasad Articles by Madhav P. Desai

16th International Conference on VLSI Design

New Delhi, India

January 04-January 08

ISBN: 0-7695-1868-0

	ASCII Text	x
	Vani Prasad, Madhav P. Desai, "Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy," VLSI Design, International Conference on, pp. 417, 16th International Conference on VLSI Design, 2003.

	BibTex	x
	@article{ 10.1109/ICVD.2003.1183171, author = {Vani Prasad and Madhav P. Desai}, title = {Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2003}, issn = {1063-9667}, pages = {417}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183171}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy SN - 1063-9667 SP EP A1 - Vani Prasad, A1 - Madhav P. Desai, PY - 2003 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Vani Prasad, Indian Institute of Technology

Madhav P. Desai, Indian Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183171

We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit. The problem can be restated as a combined buffer insertion, buffer sizing and wire sizing problem. We propose a simple buffering architecture for this problem and show that this architecture achieves a near optimal solution. We also derive simple models for a buffered wire which are suitable for high level design.

Citation:

Vani Prasad, Madhav P. Desai, "Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy," vlsid, pp.417, 16th International Conference on VLSI Design, 2003

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.