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16th International Conference on VLSI Design
Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs
New Delhi, India
January 04-January 08
ISBN: 0-7695-1868-0
Hideyuki Ichihara, Hiroshima City University
Kozo Kinoshita, Osaka Gakuin University
Koji Isodono, SHARP Corporation
Shigeki Nishikawa, SHARP Corporation
A narrow channel width between a circuit under test and a tester increases the testing time. In this paper, we propose a channel width compression method when the channel width is limited. A given test sequence is partitioned into sub-sequences, whose widths can be compressed under the limited width. Each sub-sequence is compressed and expanded by a proposed dynamically re-configurable circuit located between the circuit under test and the tester. Since the hardware overhead depends on the number of partitions for a test sequence, a procedure to partition a given test sequence into a minimum number of sub-sequences under the channel width limitation is proposed. Experimental results show that our method can compress the width of a test sequence into a half through a quarter with a relatively small number of partitions.
Citation:
Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa, "Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs," vlsid, pp.329, 16th International Conference on VLSI Design, 2003
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