DESIGN OF A HIGH SPEED STRING MATCHING CO-PROCESSOR FOR NLP

V
VLSID
2003
16th International Conference on VLSI Design
Abstract - DESIGN OF A HIGH SPEED STRING MATCHING CO-PROCESSOR FOR NLP

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	Similar Articles Articles by Vadali Srinivasa Murty Articles by P. C. Reghu Raj Articles by S. Raman

16th International Conference on VLSI Design

New Delhi, India

January 04-January 08

ISBN: 0-7695-1868-0

	ASCII Text	x
	Vadali Srinivasa Murty, P. C. Reghu Raj, S. Raman, "DESIGN OF A HIGH SPEED STRING MATCHING CO-PROCESSOR FOR NLP," VLSI Design, International Conference on, pp. 183, 16th International Conference on VLSI Design, 2003.

	BibTex	x
	@article{ 10.1109/ICVD.2003.1183134, author = {Vadali Srinivasa Murty and P. C. Reghu Raj and S. Raman}, title = {DESIGN OF A HIGH SPEED STRING MATCHING CO-PROCESSOR FOR NLP}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2003}, issn = {1063-9667}, pages = {183}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183134}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - DESIGN OF A HIGH SPEED STRING MATCHING CO-PROCESSOR FOR NLP SN - 1063-9667 SP EP A1 - Vadali Srinivasa Murty, A1 - P. C. Reghu Raj, A1 - S. Raman, PY - 2003 KW - Approximate match KW - Perfect match KW - Memory interleaving KW - NLP co-processor. VL - 0 JA - VLSI Design, International Conference on ER -

Vadali Srinivasa Murty, Indian Institute of Technology Madras

P. C. Reghu Raj, Indian Institute of Technology Madras

S. Raman, Indian Institute of Technology Madras

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183134

In Natural Language Processing applications, string matching is the main time-consuming operation. A dedicated co-processor for string matching that uses memory interleaving and parallel processing techniques can relieve the host CPU from this burden. This paper reports the FPGA design of such a system with m parallel matching units. It has been shown to improve the performance by a factor of nearly m, without increasing the chip area by more than 45%. The time complexity of the proposed algorithm is O(log₂ n), where n is the number of lexical entries. The memory used by the lexicon has been efficiently organized and the space saving achieved is about 67%.

Index Terms:

Approximate match, Perfect match, Memory interleaving, NLP co-processor.

Citation:

Vadali Srinivasa Murty, P. C. Reghu Raj, S. Raman, "DESIGN OF A HIGH SPEED STRING MATCHING CO-PROCESSOR FOR NLP," vlsid, pp.183, 16th International Conference on VLSI Design, 2003

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