16th International Conference on VLSI Design Effects of Multi-cycle Sensitization on Delay Tests New Delhi, India January 04-January 08 ISBN: 0-7695-1868-0
Existing delay test generation techniques focus on test generation for combinational blocks, and assume the inputs and outputs of the block to be unconstrained. Test application for delay tests is done by means of enhanced scan, scan shifting or functional justification; all these techniques impose minimal constraints on the inputs and the outputs of the combinational block targeted. This leads to over-testing the components for delay defects [11]. This paper analyzes the gains associated with determining the multi-cycle (sequential) sensitization of delay tests. The advantages of determining multi-cycle sensitization is then illustrated on benchmark designs with and without a delay-specific fault model.
Citation:
Arun Krishnamachary, Jacob A. Abraham, "Effects of Multi-cycle Sensitization on Delay Tests," vlsid, pp.137, 16th International Conference on VLSI Design, 2003 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||