16th International Conference on VLSI Design
High Level Modeling and Validation Methodologies for Embedded Systems: Bridging the Productivity Gap (PDF)
New Delhi, India January 04-January 08 ISBN: 0-7695-1868-0
Citation:
Sandeep K. Shukla, Jean Pierre Talpin, Stephen A. Edwards, Rajesh K. Gupta, "High Level Modeling and Validation Methodologies for Embedded Systems: Bridging the Productivity Gap," vlsid, pp.9, 16th International Conference on VLSI Design, 2003 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||