Switching Noise Analysis Framework For High Speed Logic Families

V
VLSID
2001
The 14th International Conference on VLSI Design (VLSID '01)
Abstract - Switching Noise Analysis Framework For High Speed Logic Families

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The 14th International Conference on VLSI Design (VLSID '01)

Bangalore, India

January 03-January 07

ISBN: 0-7695-0831-6

	ASCII Text	x
	M. Delaurenti, M. Graziano, G. Masera, G. Piccinini, M. Zamboni, "Switching Noise Analysis Framework For High Speed Logic Families," VLSI Design, International Conference on, pp. 524, The 14th International Conference on VLSI Design (VLSID '01), 2001.

	BibTex	x
	@article{ 10.1109/ICVD.2001.902711, author = {M. Delaurenti and M. Graziano and G. Masera and G. Piccinini and M. Zamboni}, title = {Switching Noise Analysis Framework For High Speed Logic Families}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2001}, issn = {1063-9667}, pages = {524}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2001.902711}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Switching Noise Analysis Framework For High Speed Logic Families SN - 1063-9667 SP EP A1 - M. Delaurenti, A1 - M. Graziano, A1 - G. Masera, A1 - G. Piccinini, A1 - M. Zamboni, PY - 2001 VL - 0 JA - VLSI Design, International Conference on ER -

M. Delaurenti, Politecnico di Torino

M. Graziano, Politecnico di Torino

G. Masera, Politecnico di Torino

G. Piccinini, Politecnico di Torino

M. Zamboni, Politecnico di Torino

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2001.902711

Switching noise in ultra deep sub-micron designs is assuming increasing proportions due to decreased rise times, scaled features sizes and interconnect complexity. Moreover, to achieve higher frequencies the use of different logic families is explored, which contribution in terms of noise generation is not completely defined yet. In this paper we report some results from a detailed simulation sequence performed to define clearly the influence of technological parameters and of the use of different logic families with respect to noise generation. The aim is to use these informations in a developing CAD tool for switching noise free placement.

Citation:

M. Delaurenti, M. Graziano, G. Masera, G. Piccinini, M. Zamboni, "Switching Noise Analysis Framework For High Speed Logic Families," vlsid, pp.524, The 14th International Conference on VLSI Design (VLSID '01), 2001

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