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The 14th International Conference on VLSI Design (VLSID '01)
Performance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering
Bangalore, India
January 03-January 07
ISBN: 0-7695-0831-6
ASCII Text
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G. Shrivastav, S. Mahapatra, V. Ramgopal Rao, J. Vasi, K.G. Anil, C. Fink, W. Hansch, I. Eisele, "Performance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering," VLSI Design, International Conference on, pp. 475, The 14th International Conference on VLSI Design (VLSID '01), 2001.
 
 
BibTex
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@article{ 10.1109/ICVD.2001.902703,
author = {G. Shrivastav and S. Mahapatra and V. Ramgopal Rao and J. Vasi and K.G. Anil and C. Fink and W. Hansch and I. Eisele},
title = {Performance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2001},
issn = {1063-9667},
pages = {475},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2001.902703},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Performance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering
SN - 1063-9667
SP
EP
A1 - G. Shrivastav,
A1 - S. Mahapatra,
A1 - V. Ramgopal Rao,
A1 - J. Vasi,
A1 - K.G. Anil,
A1 - C. Fink,
A1 - W. Hansch,
A1 - I. Eisele,
PY - 2001
VL - 0
JA - VLSI Design, International Conference on
ER -
 
G. Shrivastav, Indian Institute of Technology
S. Mahapatra, Indian Institute of Technology
V. Ramgopal Rao, Indian Institute of Technology
J. Vasi, Indian Institute of Technology
K.G. Anil, Universitaet der Bundeswehr
C. Fink, Universitaet der Bundeswehr
W. Hansch, Universitaet der Bundeswehr
I. Eisele, Universitaet der Bundeswehr
A comprehensive study has been performed to optimize the electrical characteristics of delta doped channel MOSFETs (D2FETs) having channel length of 60 nm. Extensive 2D device simulations have been employed to show that D2FETs exhibit higher drain current drive and reduced short channel and hot carrier effects compared to MOSFETs having uniform channel doping. The improvement has been found significant when the delta peak is shifted near the source end of the channel. Device simulations show acceptable short channel effects for 60 nm D2FETs when the gate oxide thickness is reduced to the 2.5-3 nm regime.
Citation:
G. Shrivastav, S. Mahapatra, V. Ramgopal Rao, J. Vasi, K.G. Anil, C. Fink, W. Hansch, I. Eisele, "Performance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering," vlsid, pp.475, The 14th International Conference on VLSI Design (VLSID '01), 2001
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