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The 14th International Conference on VLSI Design (VLSID '01)
Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates
Bangalore, India
January 03-January 07
ISBN: 0-7695-0831-6
Mayukh Bhattacharya, The University of Michigan
Pinaki Mazumder, The University of Michigan
Ronald J. Lomax, The University of Michigan
The finite-difference transmission line matrix (FD-TLM) method allows us to model the electromagnetic behavior of a circuit based on material properties and package dimensions, without the necessity of circuit parasitic extraction. In this paper, we extend the FD-TLM method to model micron-scale heterojunction bipolar transistors (HBTs) enabling us to perform time-domain, three-dimensional full-wave analysis of high-speed digital circuits containing HBTs. The accuracy of our HBT model is established by comparing with results of SPICE simulation using the modified Gummel-Poon BJT model. We present simulation results of a two-stage resistor-transistor logic (RTL) inverter chain and also a current-mode logic (CML) buffer circuit and compare the FD-TLM simulation result with SPICE. By keeping the interconnect lengths short, we ensure a fair comparison between the two simulation methods.
Citation:
Mayukh Bhattacharya, Pinaki Mazumder, Ronald J. Lomax, "Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates," vlsid, pp.470, The 14th International Conference on VLSI Design (VLSID '01), 2001
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