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The 14th International Conference on VLSI Design (VLSID '01)
Accurate Power Macro-modeling Techniques for Complex RTL Circuits
Bangalore, India
January 03-January 07
ISBN: 0-7695-0831-6
Nachiketh R. Potlapally, Rutgers University
Michael S. Hsiao, Rutgers University
This paper presents novel techniques for the cycle-accurate power macro-modeling of complex RTL components. The proposed techniques are based on the observation that RTL components often exhibit significantly different "power behavior" for different parts of the input space, making it difficult for a single conventional macro-model to accurately estimate the power dissipation over the entire input space. We address this problem by identifying and separating the input space into regions that display "similar" power behavior. We refer to these regions as the power modes of the component. We then construct separate macro-models for each region, and construct a function that, given the input trace to the component, selects an appropriate power mode (and hence macro-model) for use in each cycle. The proposed ideas are complementary to, and improve upon, previously proposed techniques for power macro-modeling such as linear regression, table look-up, power sensitivity, etc. We present experimental results on several practical complex RTL components, and demonstrate that the proposed techniques result in significant reductions (up to 90 %) in the error of RTL macro-modeling compared to a gate-level power estimator.
Citation:
Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar, "Accurate Power Macro-modeling Techniques for Complex RTL Circuits," vlsid, pp.235, The 14th International Conference on VLSI Design (VLSID '01), 2001
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