A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification

V
VLSID
2001
The 14th International Conference on VLSI Design (VLSID '01)
Abstract - A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification

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	Similar Articles Articles by Jian-Kun Zhao Articles by Jeffrey A. Newquist Articles by Janak H. Patel

The 14th International Conference on VLSI Design (VLSID '01)

Bangalore, India

January 03-January 07

ISBN: 0-7695-0831-6

	ASCII Text	x
	Jian-Kun Zhao, Jeffrey A. Newquist, Janak H. Patel, "A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification," VLSI Design, International Conference on, pp. 163, The 14th International Conference on VLSI Design (VLSID '01), 2001.

	BibTex	x
	@article{ 10.1109/ICVD.2001.902656, author = {Jian-Kun Zhao and Jeffrey A. Newquist and Janak H. Patel}, title = {A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2001}, issn = {1063-9667}, pages = {163}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2001.902656}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification SN - 1063-9667 SP EP A1 - Jian-Kun Zhao, A1 - Jeffrey A. Newquist, A1 - Janak H. Patel, PY - 2001 VL - 0 JA - VLSI Design, International Conference on ER -

Jian-Kun Zhao, University of Illinois at Urbana Champaign

Jeffrey A. Newquist, University of Illinois at Urbana Champaign

Janak H. Patel, University of Illinois at Urbana Champaign

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2001.902656

This paper presents a new graph traversal based framework for sequential logic implication called GRAPH SIMP. Due to the prohibitive time and space cost, few previous work target the discovery of sequential indirect implications that span multiple time frames. By using an efficient graph data structure and incorporating a graph reduction step into the implication generation process, our approach provides an efficient support for sequential implication. Sequential logic implication has many useful applications, one of which is sequentially redundant fault identification. We show that sequential implications found by GRAPH SIMP allow us to find more sequential redundancies than previously reported. Results of testing our implication algorithm against ISCAS89 circuits show that high implication coverage is essential to identifying redundant faults.

Citation:

Jian-Kun Zhao, Jeffrey A. Newquist, Janak H. Patel, "A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification," vlsid, pp.163, The 14th International Conference on VLSI Design (VLSID '01), 2001

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