Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique

V
VLSID
2001
The 14th International Conference on VLSI Design (VLSID '01)
Abstract - Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique

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The 14th International Conference on VLSI Design (VLSID '01)

Bangalore, India

January 03-January 07

ISBN: 0-7695-0831-6

	ASCII Text	x
	Anupam Datta, Sidharth Choudhury, Anupam Basu, Hiroyuki Tomiyama, Nikil Dutt, "Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique," VLSI Design, International Conference on, pp. 97, The 14th International Conference on VLSI Design (VLSID '01), 2001.

	BibTex	x
	@article{ 10.1109/ICVD.2001.902646, author = {Anupam Datta and Sidharth Choudhury and Anupam Basu and Hiroyuki Tomiyama and Nikil Dutt}, title = {Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2001}, issn = {1063-9667}, pages = {97}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2001.902646}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique SN - 1063-9667 SP EP A1 - Anupam Datta, A1 - Sidharth Choudhury, A1 - Anupam Basu, A1 - Hiroyuki Tomiyama, A1 - Nikil Dutt, PY - 2001 VL - 0 JA - VLSI Design, International Conference on ER -

Anupam Datta, Indian Institute of Technology, Kharagpur

Sidharth Choudhury, Indian Institute of Technology, Kharagpur

Anupam Basu, Indian Institute of Technology, Kharagpur

Hiroyuki Tomiyama, University of California, Irvine

Nikil Dutt, University of California, Irvine

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2001.902646

In multi-tasking preemptive real-time systems, a tighter estimate of the Worst Case Response Time(WCRT)s of the tasks can be obtained if the layout of the tasks is taken into account in the analysis. This is because the Cache Related Preemption Delay(CRPD) depends on the inter-task interference in the cache. We present an ILP formulation and an algorithm for generating a layout of the tasks such that the timing constraints of all the tasks are met. An attempt is made to generate a layout such that the CRPD is reduced for all the tasks. The performance of the proposed formulation is demonstrated.

Citation:

Anupam Datta, Sidharth Choudhury, Anupam Basu, Hiroyuki Tomiyama, Nikil Dutt, "Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique," vlsid, pp.97, The 14th International Conference on VLSI Design (VLSID '01), 2001

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