In this paper, we expose a new technique for the analysis of design flows. The modern-day chip design process is a complex one, with the following characteristics: (a) the execution times of individual tasks are difficult to predict, since a tool may occasionally produce unsatisfactory results, requiring the designer to repeat the task, (b) the increasing pressure on the project management to cut down the time-to-market forces the management to employ concurrent design techniques, and (c) the VLSI design flow is hierarchical, and a completely flat representation of the design flow is too complex to analyze. Existing techniques for design flow analysis cannot deal with the problems mentioned above. The Hierarchical Concurrent Flow Graph (HCFG) presented in this paper is an analysis technique which borrows the idea of graph transmittance from circuit theory and extends the concept to include hierarchy, concurrency and stochastic variation in task execution times. We apply the HCFG technique to analyze two realistic design flows. We show that a project manager can carry out a pre-execution "what-if" analysis to determine the best design flow management strategy, that is most likely to lead to the lowest execution time.