An Efficient Hierarchical Fault Isolation Technique for Mixed-Signal Boards

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	Similar Articles Articles by Sasikumar Cherubal Articles by Abhijit Chatterjee

13th International Conference on VLSI Design

Calcutta, India

January 04-January 07

ISBN: 0-7695-0487-6

	ASCII Text	x
	Sasikumar Cherubal, Abhijit Chatterjee, "An Efficient Hierarchical Fault Isolation Technique for Mixed-Signal Boards," VLSI Design, International Conference on, pp. 550, 13th International Conference on VLSI Design, 2000.

	BibTex	x
	@article{ 10.1109/ICVD.2000.812665, author = {Sasikumar Cherubal and Abhijit Chatterjee}, title = {An Efficient Hierarchical Fault Isolation Technique for Mixed-Signal Boards}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2000}, issn = {1063-9667}, pages = {550}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812665}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - An Efficient Hierarchical Fault Isolation Technique for Mixed-Signal Boards SN - 1063-9667 SP EP A1 - Sasikumar Cherubal, A1 - Abhijit Chatterjee, PY - 2000 KW - Fault isolation KW - mixed-signal boards KW - fault verification VL - 0 JA - VLSI Design, International Conference on ER -

Sasikumar Cherubal, Georgia Institute of Technology

Abhijit Chatterjee, Georgia Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812665

In this paper, we describe a technique for hierarchical fault isolation in analog and mixed-signal circuit boards. The technique is based on verifying the fault-free behavior of partitions of the circuit, and can be applied hierarchically to large systems. The technique is shown to be independent of the availability/completeness of fault models for the Circuit-Under-Test (CUT). Also, it has minimal on-line computational requirements and can be easily programmed on an automatic tester. Experimental results to show the effectiveness of the technique are presented

Index Terms:

Fault isolation, mixed-signal boards, fault verification

Citation:

Sasikumar Cherubal, Abhijit Chatterjee, "An Efficient Hierarchical Fault Isolation Technique for Mixed-Signal Boards," vlsid, pp.550, 13th International Conference on VLSI Design, 2000

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