Testing of sequential circuits requires that test patterns are applied in a specific sequence only. On-chip test pattern generators often suffer from the problem that it requires incorporation of idle cycles between the test patterns. In this paper we present a scheme that can generate any given sequence of test patterns using a scheme based on Cellular Automata (CA) and some associated circuitry without any inserted idle cycles. This also results in up to 95% reduction in the memory requirement over the direct storage of the patterns. Moreover, regular, modular and cascadable structure of CA with local interconnections make the scheme ideally suited for VLSI implementation. The test application hardware has been specified in Verilog, simulated for functional correctness and synthesized using Synergy -- the CAD tool from Cadence.