loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
13th International Conference on VLSI Design
Timing Analysis with Implicitly Specified False Paths
Calcutta, India
January 04-January 07
ISBN: 0-7695-0487-6
Eugene Goldberg, Cadence Berkeley Labs
Alexander Saldanha, Cadence Berkeley Labs
We consider the problem of timing analysis in the presence of known false paths. The main difficulty in adaptation of classical breadth-first search to the problem is that at each node one has to store the number of delays which is proportional to that of false paths going through the node. We propose a reduction technique that allows one to drastically reduce the number of delays to store. In particular, the technique can be applied when false paths are implicitly specified by a set of through-path exceptions or false sub- graphs. In addition, we introduce a new data structure for representing false paths called abstract false graphs which are as expressive as false sub-graphs but are as compact as through-path exceptions. A preliminary prototype implementation illustrates the potential benefits of our reduction technique by showing up to exponential reduction in memory usage and run-time over previous work.
Index Terms:
timing analysis, breadth-first search, known false paths, implicit false path representation
Citation:
Eugene Goldberg, Alexander Saldanha, "Timing Analysis with Implicitly Specified False Paths," vlsid, pp.518, 13th International Conference on VLSI Design, 2000
Usage of this product signifies your acceptance of the Terms of Use.