This paper introduces the concept of using synthesizable RTL blocks as ASIC memories and presents them as an alternative to compiler (hard-macro type) memories that are not optimized for implementation at lower-end configurations. The main advantages of these synthesizable memories are reduced area, reduced development cycle time and increased design flexibility in terms of meeting target performance and obtaining the desired physical configuration. Experimental results show that replacing lower end compiler macros with their synthesized counterpart can lead to a memory area reduction of up to 37% in a 800K gates ASIC design, while meeting all the timing requirements for the design.