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13th International Conference on VLSI Design
A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores
Calcutta, India
January 04-January 07
ISBN: 0-7695-0487-6
ASCII Text
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Karthikeyan Madathil, Jagdish C Rao, Subash Chander, Amitabh Menon, Avinash K Gautam, Amit M Brahme, H. Udayakumar, "A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores," VLSI Design, International Conference on, pp. 468, 13th International Conference on VLSI Design, 2000.
 
 
BibTex
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@article{ 10.1109/ICVD.2000.812651,
author = {Karthikeyan Madathil and Jagdish C Rao and Subash Chander and Amitabh Menon and Avinash K Gautam and Amit M Brahme and H. Udayakumar},
title = {A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2000},
issn = {1063-9667},
pages = {468},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812651},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Design, International Conference on
TI - A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores
SN - 1063-9667
SP
EP
A1 - Karthikeyan Madathil,
A1 - Jagdish C Rao,
A1 - Subash Chander,
A1 - Amitabh Menon,
A1 - Avinash K Gautam,
A1 - Amit M Brahme,
A1 - H. Udayakumar,
PY - 2000
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Karthikeyan Madathil, Texas Instruments (India) Ltd.
Jagdish C Rao, Texas Instruments (India) Ltd.
Subash Chander, Texas Instruments (India) Ltd.
Amitabh Menon, Texas Instruments (India) Ltd.
Avinash K Gautam, Texas Instruments (India) Ltd.
Amit M Brahme, Texas Instruments (India) Ltd.
H. Udayakumar, Texas Instruments (India) Ltd.
The TI T320C27XX DSP Core is primarily targeted at the high-end Control Market, a typical application being the hard-disk drive. Different end- equipment segments in such a market demand varying requirements for cost and performance of the processor Core. This forces certain customization in our design and design methodology to satisfy these varying requirements. A capability to perform quick cost versus performance tradeoffs in a design flow becomes imperative. This paper presents the framework used to meet this range of design requirements by controlling and constraining certain parameters that influence the cost and performance of a design.
Citation:
Karthikeyan Madathil, Jagdish C Rao, Subash Chander, Amitabh Menon, Avinash K Gautam, Amit M Brahme, H. Udayakumar, "A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores," vlsid, pp.468, 13th International Conference on VLSI Design, 2000
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