State-Machine Based Logic Simulation Using Three Logic Values

V
VLSID
2000
13th International Conference on VLSI Design
Abstract - State-Machine Based Logic Simulation Using Three Logic Values

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13th International Conference on VLSI Design

Calcutta, India

January 04-January 07

ISBN: 0-7695-0487-6

	ASCII Text	x
	Peter M. Maurer, William J. Schilp, "State-Machine Based Logic Simulation Using Three Logic Values," VLSI Design, International Conference on, pp. 430, 13th International Conference on VLSI Design, 2000.

	BibTex	x
	@article{ 10.1109/ICVD.2000.812645, author = {Peter M. Maurer and William J. Schilp}, title = {State-Machine Based Logic Simulation Using Three Logic Values}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2000}, issn = {1063-9667}, pages = {430}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812645}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - State-Machine Based Logic Simulation Using Three Logic Values SN - 1063-9667 SP EP A1 - Peter M. Maurer, A1 - William J. Schilp, PY - 2000 KW - Logic Simulation KW - Discrete Simulation VL - 0 JA - VLSI Design, International Conference on ER -

Peter M. Maurer, University of Southern Florida

William J. Schilp, University of Southern Florida

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812645

The Inversion Algorithm is an event-driven logic simulation technique that is competitive with Levelized Compiled Code Simulation even at extremely high activity levels. Previous versions of the algorithm have been limited to two-valued simulation. The three-valued Inversion Algorithm represents a radical redesign of the algorithm to permit three-valued simulation. The three-valued scheduling technique is significantly more complex than that of the two-valued algorithm, as is the procedure for collapsing simultaneous events. The three-valued algorithm is also capable of converting portions of the simulation from three-valued to two-valued, once stable binary values have been achieved. This permits significant enhancements in the performance of the algorithm. Experimental data shows that, like the two-valued algorithm, the three-valued algorithm is competitive with two-valued levelized compiled code simulation.

Index Terms:

Logic Simulation, Discrete Simulation

Citation:

Peter M. Maurer, William J. Schilp, "State-Machine Based Logic Simulation Using Three Logic Values," vlsid, pp.430, 13th International Conference on VLSI Design, 2000

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